1. Field of the Invention
This invention relates to a circuit arrangement for generating a pulse width modulation (PWM) signal having a pulse width in accordance with logic of a digital signal.
2. Related Background Art
Since PWM (pulse width modulation) waveform generating circuits are widely used in various kinds of electronic circuits like a DC-DC converter (a switching power source), it is advantageous for an entire system to reduce the area occupied of the circuit and decrease its power consumption.
FIG. 1 is a block diagram of a conventional PWM waveform generating circuit, which shows an example configured to generate a PWM signal of a duty ratio in accordance with the logic of a 6-bit digital signal.
The PWM waveform generating circuit of FIG. 1 includes a ring oscillator 1 connecting 64 pieces of buffers BF in series, multiplexer (MUX) for selecting one of outputs of the buffers BF of different stages in the ring oscillator 1, change detecting circuit 3 for detecting a logic changing position of outputs from the ring oscillator 1, change detecting circuit 4 for detecting a logic changing position of output from the multiplexer 2, and RS flip-flop 5.
FIGS. 2a is a diagram explaining operational principle of the multiplexer 2, which shows an example configured to select one of 26=64 kinds of input signals A0 through A63 according to the logic of 6-bit select signals D0 through D5. Among these select signals D0 through D5, if the least significant bit is D0 and the most significant bit is D5, then the numerical value M showing the select signals D0 through D5 is expressed by Equation (1).
M=D5xc3x9725+D4xc3x9724+D3xc3x9723+D2xc3x9722+D1xc3x972+D0xe2x80x83xe2x80x83(1)
As shown by the bold line in FIG. 2a, when the input signal A3 is selected, for example, selecting signals (D5, D4, D3, D2, D1, D0) may be determined as (0, 0, 0, 0, 1, 1). That is, the decimal value of these selection signals is xe2x80x9c3xe2x80x9d.
In this specification, it is assumed that the multiplexer performs selection in the same manner as shown in FIG. 2a independently from signal names of selections signals or input signals. For example, FIG. 2b shows an example in which different kinds of input signals (C0, C1, B5, B0, A4, . . . , Ro, F11) having T0 as the least significant bit and S5 as the most significant bit are inputted. For example, in case of (S5, S4, S3, S2, S1, S0, T0)=(0, 0, 0, 0, 1, 0), the third input signal B5 from the left end is selected as shown in FIG. 2b. 
As shown in FIG. 3a in detail, the change detecting circuit 3 of FIG. 1 includes a delay circuit 6 for delaying a signal by a time approximately equal to the signal propagation delay time of the multiplexer 2, even numbered pieces of inverters 7 connected in series, and an EXOR gate 8, and output from the change detecting circuit 3 is inputted to a set terminal S of the RS flip-flop 5. Similarly, the change detecting circuit 4, shown in detail in FIG. 3b, includes an even numbered pieces of inverters 9 connected in series and an EXOR gate 10, and output from the change detecting circuit 4 is inputted to a reset terminal R of the RS flip-flop 5.
Output from the final-stage buffer BF in the ring oscillator 1 is inverted by a NAND gate G1, and thereafter fed back to the first-stage buffer BF. When the active terminal connected to the input terminal of the NAND gate G1 is set HIGH level, a stable status is lost, and the ring oscillator 1 oscillates. In contrast, when the active terminal is set LOW level, outputs from all of the buffers BF in respective stages become HIGH level, and oscillation stops. Although the active terminal is not indispensable, it is often provided in order to output a PWM signal only when required, for the purpose of reducing the power consumption.
There are no specific limitations for the number of bits of the digital signal inputted to the multiplexer 2 and the number of stages of buffers BF in the ring oscillator 1.
FIG. 4 is a timing diagram of respective portions in the PWM waveform generating circuit of FIG. 1. Shown in FIG. 4 are the waveform of output A from the ring oscillator 1, output waveform of the first-stage buffer BF, output waveform of the second-stage buffer BF, output waveform of the third-stage buffer BF, output waveform of the 33rd-stage buffer BF, output waveforms of the change detecting circuits 3 and 4, and output waveform of the RS flip-flop 5.
Behaviors of the circuit of FIG. 1 are explained below with reference to the tiling diagram of FIG. 4. Buffers BF in respective stages in the ring oscillator 1 each deliver the output signal of the first-stage buffer BF to the next buffer BF while delaying it by a predetermined time. The output signal from the final-stage buffer BF is inverted in phase by the NAND gate 11, and then inputted to the first-stage buffer BF.
The multiplexer 2 selects one of outputs from the buffers BF in the ring oscillator 1, based on the logic of the digital signal S0xcx9cS5.
The change detecting circuit 3 detects the rising edge and the falling edge of the output from the ring oscillator 1 and outputs a narrow-width pulse at time when each edge is detected. The change detecting circuit 4 detects the rising edge and the falling edge of the output from the multiplexer 2 and outputs a narrow-width pulse at time when each edge is detected.
For example, on the assumption that the output A from the ring oscillator 1 changes to HIGH level at time T1 of FIG. 4, the change detecting circuit 3 outputs a positive pulse lasting from time T1 to T2. Here, if bits of the digital signal is (1,0,0,0,0,0), then the output of the 33rd-stage buffer BF is selected by the multiplexer 2, and the change detecting circuit 4 outputs a positive pulse lasting from time T3 to T4. As a result, the RS flip-flop 5 is set at time T1, and reset at time T3. That is, the RS flip-flop 5 outputs a PWM signal having the pulse width lasting from time T1 to T3.
Similarly, the change detecting circuit 3 outputs a positive pulse lasting from time T5 to T6, and the change detecting circuit 4 outputs a positive pulse lasting from time T7 to T8. Therefore, the RS flip-flop 5 is set at time T5 and reset at time T7.
In case of arranging the PWM waveform generating circuit of FIG. 1 by using CMOS process, the circuit size of the ring oscillator 1 becomes large because each of the buffers BF in the ring oscillator 1 is made up of two inverters. For example, when buffers BF of 64 stages are connected in series, twice the stages of the buffers, that is, inverters of 128 stages must be connected. Such a large circuit size makes it difficult to miniaturize a system containing the circuit of FIG. 1, and increases its power consumption.
It is therefore an object of the present invention to provide a pulse width modulation waveform generating circuit that it is possible to reduce circuit size and power consumption.
To attain the object, a pulse width modulation waveform generating circuit for generating 2n kinds of pulse width modulation signals having different pulse widths in accordance with a digital signal of n (n is an integer equal to or more than 2) bits, comprising:
oscillating signal output means for having m (m is an integer equal to or more than 2) pieces of first inverting means connected in series to each other, each of these first inverting means outputting an oscillating signal with a phase different from each other;
selecting means for selecting one of signals in accordance with each of output signals of said m pieces of first inverting means connected in series, based on at least partial bits of said digital signal of n bits, and
pulse generating means for generating said pulse width modulation signal having a pulse width in accordance with the signal selected by said selecting means.
According to the present invention, since the oscillating signal output means is constituted by serially connecting a plurality of inverters and generate a pulse width modulation signal based on output of each inverter in the oscillating signal output means, it is possible to reduce circuit size and power consumption.
Additionally, when outputs from inverters of odd-numbered stages in the ring oscillator are regarded as signals delaying in phase by more than a half cycle from the output of the ring oscillator, these outputs from the inverters of odd-numbered stages need not be inverted, and this enables further reduction of the circuit size.
Furthermore, by providing a pulse generating means capable of generating one of different kinds of pulse width modulation signals as many as twice or four times the number of connected stages of inverters in the ring oscillator, it is possible to simplify structure of the ring oscillator and reduce circuit size and power consumption.